Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide a system and method for adjusting one or more thresholds to achieve input and output power balance. Merely by way of example, some embodiments of the invention have been applied to buck converters. But it would be recognized that the invention has a much broader range of applicability.
In recent years, with the development of integrated circuit and information technology, a variety of battery-powered portable electronic devices, such as mobile phones, digital cameras, and notebook computers, became increasingly popular. These battery-powered portable electronic devices raise the need for high-performance power-management chips with low cost, high efficiency and good transient characteristics.
Among conventional power management chips, a chip for DC-DC power converter often is one of the most widely used. A buck converter usually is one type of DC-DC power converter, and has been used to convert a high input voltage to a low output voltage. There are various types of buck converters, such as a current-mode buck converter, a voltage-mode buck converter, and a hysteresis-mode buck converter.
FIG. 1 is a simplified diagram of a conventional current-mode buck converter. The current-mode buck converter 100 includes an error amplifier 110, a compensation network 112, a comparator 114, a logic controller 120, an SR flip-flop 122, an oscillator 124, drivers 130 and 134, power transistors 140 and 144, an output filter inductor 150, an output filter capacitor 160, resistors 170 and 172, and a sensing circuit 190. The SR flip-flop 122 includes two NOR gates.
For example, the error amplifier 110, the compensation network 112, the comparator 114, the logic controller 120, the SR flip-flop 122, the oscillator 124, the drivers 130 and 134, the sensing circuit 190, and the power transistors 140 and 144 are on a chip 198. In another example, the output filter inductor 150, the output filter capacitor 160, and the resistors 170 and 172 are off the chip 198.
As shown in FIG. 1, the transistor 140 is a PMOS transistor including a drain terminal, and the transistor 144 is an NMOS transistor including a drain terminal. The drain terminal of the PMOS transistor 140 and the drain terminal of the NMOS transistor 144 are connected. The inductor 150 includes two terminals. One terminal of the inductor 150 is connected to the drain terminal of the PMOS transistor 140 and the drain terminal of the NMOS transistor 144, and the other terminal of the inductor 150 is at an output voltage 182.
An input voltage 180 is received by the current-mode buck converter 100, which in response generates the output voltage 182 and an output current 188. The output voltage 182 is converted into a feedback voltage 184 by a voltage divider including the resistors 170 and 172, and the feedback voltage 184 is proportional to the output voltage 182. The feedback voltage 184 is received by a negative input terminal of the error amplifier 110, and a reference voltage 186 is received by a positive input terminal of the error amplifier 110. The error amplifier 110 generates, together with the compensation network 112, a compensation voltage 111 based at least in part on the feedback voltage 184 and the reference voltage 186. The compensation network 112 performs loop phase compensation. If the feedback voltage 184 increases and the reference voltage 186 remains unchanged, the compensation voltage 111 decreases. Additionally, if the feedback voltage 184 decreases and the reference voltage 186 remains unchanged, the compensation voltage 111 increases.
The sensing circuit 190 detects a current that flows through the power transistor 140 and generates a current-sensing voltage 191. The current-sensing voltage 191 represents the magnitude of the current that flows through the power transistor 140. Additionally, the current-sensing voltage 191 and the compensation voltage 111 are received by the comparator 114, which in response generates a comparison signal 115. Also, the oscillator 124 generates a clock signal 125. For example, the clock signal 125 determines the time when the power transistor 140 becomes turned on.
The clock signal 125 is received by a set terminal of the SR flip-flop 122, and the comparison signal 115 is received by a reset terminal of the SR flip-flop 122. In response, the SR flip-flop 122 generates a pulse-width-modulation signal 123, and outputs the pulse-width-modulation signal 123 to the logic controller 120. The logic controller 120 generates logic signals 131 and 135 based at least in part on the pulse-width-modulation signal 123. The logic signal 131 is received by the driver 130, which in response outputs a drive signal 133 to turn on or off the power transistor 140. Additionally, the logic signal 135 is received by the driver 134, which in response outputs a drive signal 137 to turn on or off the power transistor 144.
For example, when the power transistor 140 becomes turned off, then after a predetermined dead-time period, the power transistor 144 becomes turned on. In another example, when the power transistor 144 becomes turned off, then after another predetermined dead-time period, the power transistor 140 becomes turned on. In yet another example, the predetermined dead-time period is equal to the another predetermined dead-time period in magnitude. In yet another example, the predetermined dead-time period is not equal to the another predetermined dead-time period in magnitude.
The power transistors 140 and 144 affect a current 151 that flows through the output filter inductor 150. When the power transistor 140 is turned on and the power transistor 144 is turned off, the current 151 is equal to the current that flows through the power transistor 140, and the magnitude of the current 151 is represented by the current-sensing voltage 191. When the power transistor 140 is turned off and the power transistor 144 is turned on, the current 151 is equal to the current that flows through the power transistor 144.
As shown in FIG. 1, the power transistor 140 is a PMOS transistor, and the power transistor 144 is an NMOS transistor. The gate terminal of the PMOS transistor 140 is connected to the driver 130, and the source terminal of the PMOS transistor 140 receives the input voltage 180. Additionally, the gate terminal of the NMOS transistor 144 is connected to the driver 134, and the source terminal of the NMOS transistor 144 is biased to the ground. Also, the drain terminal of the PMOS transistor 140 and the drain terminal of the NMOS transistor 144 both are connected to one terminal of the output filter inductor 150. The other terminal of the output filter inductor 150 is connected to one terminal of the output filter capacitor 160, and the other terminal of the output filter capacitor 160 is grounded.
FIG. 2 is a simplified conventional timing diagram for the current-mode buck converter 100. The waveform 225 represents the clock signal 125 as a function of time, the waveform 211 represents the compensation voltage 111 as a function of time, and the waveform 291 represents the current-sensing voltage 191 as a function of time. Additionally, the waveform 223 represents the pulse-wide-modulation signal 123 as a function of time, and the waveform 251 represents the current 151 as a function of time.
When the power transistor 140 becomes turned off, then after a predetermined dead-time period, the power transistor 144 becomes turned on. For example, the predetermined dead-time period is relatively short, so effect of the predetermined dead-time period is not shown in FIG. 2. Additionally, when the power transistor 144 becomes turned off, then after another predetermined dead-time period, the power transistor 140 becomes turned on. In another example, the another predetermined dead-time period is relatively short, so effect of the another predetermined dead-time period is not shown in FIG. 2.
At time t1, the clock signal 125 changes from a logic low level to a logic high level as shown by the waveform 225, and pulse-width-modulation signal 123 changes from a logic low level to a logic high level as shown by the waveform 223. In response, at time t1, the power transistor 144 becomes turned off and the power transistor 140 becomes turned on to supply energy to the output. Also, at time t1, the current-sensing voltage 191 rises rapidly as shown by the waveform 291.
From time t1 to time t2, the current-sensing voltage 191 increases gradually (e.g., increases gradually and linearly) as shown by the waveform 291 and the current 151 also increases gradually (e.g., increases gradually and linearly) as shown by the waveform 251. At time t2, the current-sensing voltage 191 reaches or exceeds the compensation voltage 111 as shown by the waveforms 291 and 211. In response, at time t2, the comparison signal changes from a logic low level to a logic high level causing he pulse-width-modulation signal 123 to change from the logic high level to the logic low level as shown the waveform 223. Additionally, at time t2, the power transistor 140 becomes turned off and the power transistor 144 becomes turned on to allow freewheeling of the output filter inductor 150. Also, at time t2, the current-sensing voltage 191 falls rapidly as shown by the waveform 291 and the current 151 starts to decrease gradually (e.g., to decrease gradually and linearly) as shown by the waveform 251.
If the output voltage 182 deviates from a desired magnitude, the compensation voltage 111 also changes. This change in the compensation voltage 111 causes the pulse width of the pulse-width-modulation signal 123 to also change in order to regulate the output voltage 182 to the desired magnitude. Additionally, the frequency of the clock signal 125 remains constant, and the switching frequency of the pulse-width-modulation signal 123 also remains constant.
FIG. 3 is a simplified diagram of a conventional voltage-mode buck converter. The voltage-mode buck converter 300 includes an error amplifier 310, a compensation network 312, a comparator 314, a logic controller 320, an SR flip-flop 322, an oscillator 324, drivers 330 and 334, power transistors 340 and 344, an output filter inductor 350, an output filter capacitor 360, and resistors 370 and 372. The SR flip-flop 322 includes two NOR gates.
For example, the error amplifier 310, the compensation network 312, the comparator 314, the logic controller 320, the SR flip-flop 322, the oscillator 324, the drivers 330 and 334, and the power transistors 340 and 344 are on a chip 398. In another example, the output filter inductor 350, the output filter capacitor 360, and the resistors 370 and 372 are off the chip 398.
As shown in FIG. 3, transistor 340 is a PMOS transistor is including a drain terminal, and the transistor 344 is an NMOS transistor including a drain terminal. The drain terminal of the PMOS transistor 340 and the drain terminal of the NMOS transistor 344 are connected. The inductor 350 includes two terminals. One terminal of the inductor 350 is connected to the drain terminal of the PMOS transistor 340 and the drain terminal of the NMOS transistor 344, and the other terminal of the inductor 350 is at an output voltage 382.
An input voltage 380 is received by the voltage-mode buck converter 300, which in response generates the output voltage 382 and an output current 388. The output voltage 382 is converted into a feedback voltage 384 by a voltage divider including the resistors 370 and 372, and the feedback voltage 384 is proportional to the output voltage 382. The feedback voltage 384 is received by a negative input terminal of the error amplifier 310, and a reference voltage 386 is received by a positive input terminal of the error amplifier 310. The error amplifier 310 generates, together with the compensation network 312, a compensation voltage 311 based at least in part on the feedback voltage 384 and the reference voltage 386. The compensation network 312 performs loop phase compensation. If the feedback voltage 384 increases and the reference voltage 386 remains unchanged, the compensation voltage 311 decreases. Additionally, if the feedback voltage 384 decreases and the reference voltage 386 remains unchanged, the compensation voltage 311 increases.
The compensation voltage 311 is received by the comparator 314, which also receives a ramping voltage 317 (e.g., a ramping voltage with a saw-tooth waveform). For example, the ramping voltage 317 is generated by the oscillator 324. In response, the comparator 314 generates a comparison signal 315. Additionally, the oscillator 324 generates a clock signal 325. For example, the clock signal 325 determines the time when the power transistor 340 becomes turned on.
The clock signal 325 is received by a set terminal of the SR flip-flop 322, and the comparison signal 315 is received by a reset terminal of the SR flip-flop 322. In response, the SR flip-flop 322 generates a pulse-width-modulation signal 323, and outputs the pulse-width-modulation signal 323 to the logic controller 320. The logic controller 320 generates logic signals 331 and 335 based at least in part on the pulse-width-modulation signal 323. The logic signal 331 is received by the driver 330, which in response outputs a drive signal 333 to turn on or off the power transistor 340. Additionally, the logic signal 335 is received by the driver 334, which in response outputs a drive signal 337 to turn on or off the power transistor 344.
For example, when the power transistor 340 becomes turned off, then after a predetermined dead-time period, the power transistor 344 becomes turned on. In another example, when the power transistor 344 becomes turned off, then after another predetermined dead-time period, the power transistor 340 becomes turned on. In yet another example, the predetermined dead-time period is equal to the another predetermined dead-time period in magnitude. In yet another example, the predetermined dead-time period is not equal to the another predetermined dead-time period in magnitude.
The power transistors 340 and 344 affect a current 351 that flows through the output filter inductor 350. When the power transistor 340 is turned on and the power transistor 344 is turned off, the current 351 is equal to the current that flows through the power transistor 340. When the power transistor 340 is turned off and the power transistor 344 is turned on, the current 351 is equal to the current that flows through the power transistor 344.
As shown in FIG. 3, the power transistor 340 is a PMOS transistor, and the power transistor 344 is an NMOS transistor. The gate terminal of the PMOS transistor 340 is connected to the driver 330, and the source terminal of the PMOS transistor 340 receives the input voltage 380. Additionally, the gate terminal of the NMOS transistor 344 is connected to the driver 334, and the source terminal of the NMOS transistor 344 is biased to the ground. Also, the drain terminal of the PMOS transistor 340 and the drain terminal of the NMOS transistor 344 both are connected to one terminal of the output filter inductor 350. The other terminal of the output filter inductor 350 is connected to one terminal of the output filter capacitor 360, and the other terminal of the output filter capacitor 360 is grounded.
FIG. 4 is a simplified conventional timing diagram for the voltage-mode buck converter 300. The waveform 425 represents the clock signal 325 as a function of time, the waveform 411 represents the compensation voltage 311 as a function of time, and the waveform 417 represents the ramping voltage 317 as a function of time. Additionally, the waveform 423 represents the pulse-width-modulation signal 323 as a function of time, and the waveform 451 represents the current 351 as a function of time.
When the power transistor 340 becomes turned off, then after a predetermined dead-time period, the power transistor 344 becomes turned on. For example, the predetermined dead-time period is relatively short, so effect of the predetermined dead-time period is not shown in FIG. 4. Additionally, when the power transistor 344 becomes turned off, then after another predetermined dead-time period, the power transistor 340 becomes turned on. In another example, the another predetermined dead-time period is relatively short, so effect of the another predetermined dead-time period is not shown in FIG. 4.
At time t11, the clock signal 325 changes from a logic low level to a logic high level as shown by the waveform 425 and the pulse-width modulation signal 323 changes from a logic low level to a logic high level as shown by the waveform 423. In response, at time t11, the power transistor 344 becomes turned off and the power transistor 340 becomes turned on to supply energy to the output.
From time t11 to time t12, the ramping voltage 317 increases gradually (e.g., increases gradually and linearly) as shown by the waveform 417 and the current 351 also increases gradually (e.g., increases gradually and linearly) as shown by the waveform 451. At time t12, the ramping voltage 317 reaches or exceeds the compensation voltage 311 as shown by the waveforms 417 and 411. In response, at time t12, the comparison signal 315 changes from a logic low level to a logic high level, causing the pulse-width-modulation signal 323 to change from the logic high level to the logic low level as shown by the waveform 423. Additionally, at time t12, the power transistor 340 becomes turned off and the power transistor 344 becomes turned on to allow freewheeling of the output filter inductor 350. Also, at time t12, the current 151 starts to decrease gradually (e.g., to decrease gradually and linearly) as shown by the waveform 451.
If the output voltage 382 deviates from a desired magnitude, the compensation voltage 311 also changes. This change in the compensation voltage 311 causes the pulse width of the pulse-width-modulation signal 323 to also change in order to regulate the output voltage 382 to the desired magnitude. Additionally, the frequency of the clock signal 325 remains constant, and the switching frequency of the pulse-width-modulation signal 323 also remains constant.
Another type of buck converter, the conventional hysteresis-mode buck converter is considered to be a simple system that can provide a rapid transient response. For example, the conventional hysteresis-mode buck converter usually does not need frequency compensation and can respond to changes in load conditions within one switching cycle.
FIG. 5 is a simplified diagram of a conventional hysteresis-mode buck converter. The hysteresis-mode buck converter 500 includes a hysteresis comparator 510, a logic controller 520, drivers 530 and 534, power transistors 540 and 544, an output filter inductor 550, an output filter capacitor 560, and resistors 570 and 572.
For example, the hysteresis comparator 510, the logic controller 520, the drivers 530 and 534, and the power transistors 540 and 544 are on a chip 598. In another example, the output filter inductor 550, the output filter capacitor 560, and the resistors 570 and 572 are off the chip 598.
As shown in FIG. 5, the transistor 540 is a PMOS transistor including a drain terminal, and the transistor 544 is an NMOS transistor including a drain terminal. The drain terminal of the PMOS transistor 540 and the drain terminal of the NMOS transistor 544 are connected. The inductor 550 includes two terminals. One terminal of the inductor 550 is connected to the drain terminal of the PMOS transistor 540 and the drain terminal of the NMOS transistor 544, and the other terminal of the inductor 550 is at an output voltage 582.
As shown in FIG. 5, an input voltage 580 is received by the hysteresis-mode buck converter 500, which in response generates the output voltage 582 and an output current 588. The output voltage 582 is converted into a feedback voltage 584 by a voltage divider including the resistors 570 and 572, and the feedback voltage 584 is proportional to the output voltage 582. The feedback voltage 584 is received by a negative input terminal of the hysteresis comparator 510, and a reference voltage 586 is received by a positive input terminal of the hysteresis comparator 510. The hysteresis comparator 510 generates a modulation signal 523, and outputs the modulation signal 523 to the logic controller 520. The logic controller 520 generates logic signals 531 and 535 based at least in part on the modulation signal 523. The logic signal 531 is received by the driver 530, which in response outputs a drive signal 533 to turn on or off the power transistor 540. Additionally, the logic signal 535 is received by the driver 534, which in response outputs a drive signal 537 to turn on or off the power transistor 544.
For example, when the power transistor 540 becomes turned off, then after a predetermined dead-time period, the power transistor 544 becomes turned on to allow freewheeling of the output filter inductor 550. In another example, when the power transistor 544 becomes turned off, then after another predetermined dead-time period, the power transistor 540 becomes turned on to supply energy to the output. In yet another example, the predetermined dead-time period is equal to the another predetermine dead-time period in magnitude. In yet another example, the predetermined dead-time period is not equal to the another predetermined dead-time period in magnitude.
The power transistors 540 and 544 affect a current 551 that flows through the output filter inductor 550. When the power transistor 540 is turned on and the power transistor 544 is turned off, the current 551 is equal to the current that flows through the power transistor 540. When the power transistor 540 is turned off and the power transistor 544 is turned on, the current 551 is equal to the current that flows through the power transistor 544.
As shown in FIG. 5, the power transistor 540 is a PMOS transistor, and the power transistor 544 is an NMOS transistor. The gate terminal of the PMOS transistor 540 is connected to the driver 530, and the source terminal of the PMOS transistor 540 receives the input voltage 580. Additionally, the gate terminal of the NMOS transistor 544 is connected to the driver 534, and the source terminal of the NMOS transistor 544 is biased to the ground. Also, the drain terminal of the PMOS transistor 540 and the drain terminal of the NMOS transistor 544 both are connected to one terminal of the output filter inductor 550. The other terminal of the output filter inductor 550 is connected to one terminal of the output filter capacitor 560, and the other terminal of the output filter capacitor 560 is grounded.
The power transistors 540 and 544 are affected by the modulation signal 523, which is generated by the hysteresis comparator 510 based at least in part on the feedback voltage 584 and the reference voltage 586. The hysteresis-mode buck converter 500 adjusts the output voltage 582 by keeping the feedback voltage 584 within the hysteresis window that has been set by the reference voltage 586 for the hysteresis comparator 510. For high input voltage 580, the output filter inductor 550 with high inductance and the output filter capacitor 560 with high capacitance often are used.
For the conventional current-mode buck converter 100 and the voltage-mode buck converter 300, the switching frequency usually is fixed and determined by an internal clock. With the fixed switching frequency, the conventional current-mode buck converter 100 and the voltage-mode buck converter 300 often encounter significant difficulties in achieving high efficiency under light load conditions. Additionally, the conventional hysteresis-mode buck converter 500 often suffers from system instability that is causes by signal noises and/or phase lags.
Hence it is highly desirable to improve the techniques of power converters.